The goal of this work is to investigate new readout circuit concepts for next generation capacitive micro-microelectromechanical systems (MEMS) accelerometers, which fulfill the automotive requirements for autonomous driving applications, including high linearity and robustness against EMI, while limiting their noise contribution and their area consumption. In this work, a top-down evaluation flow is defined using different abstraction levels for the verification of the readout circuit architectures. This flow enables to rapidly compare several architectures and to highlight their attributes. Furthermore, it permits to uncover architectural issues early in the design phase so that these can be solved ahead of transistor-level design.
